Phase lock loop (PLL) circuits are used in high-speed communication devices and electronic testing instruments to generate a continuous wave signal at a precise and stable frequency. Phase lock loop circuits generally include a reference frequency, a synthesizer and a voltage controlled oscillator (VCO). Two known synthesizers used in PLL circuits are the integer N synthesizer and fractional N synthesizer. Integer N synthesis utilizes whole integer multiples of a reference frequency to synthesize the output frequency thus providing a coarser resolution than fractional N synthesis, which utilizes fractional levels for a finer resolution.
Reducing lock time in a PLL circuit is always of importance in the design of high-speed communication devices. Reduction of lock time requires minimization of transient responses occurring in the PLL circuit. One technique for reducing lock time includes the use of a regular speed (normal) charge pump and a faster speed (adapt) charge pump in a fractional N synthesizer to provide for speedier signal acquisition. Unfortunately, the use of two different charge pumps generates a transition discontinuity, also referred to as a transition glitch, which can negatively impact lock time. The transition glitch increases the transient response for the PLL circuit, thereby also increasing the lock time for the PLL circuit.
Approaches have been suggested to overcome the problem of reducing the transient response in the PLL circuit. However, so far these approaches have been limited to PLL circuits having a constant VCO gain. PLL circuits using the abovementioned technique may exhibit different transient responses when the PLL circuit uses multiple VCOs. Furthermore, for some oscillators, the transient response of the PLL may vary depending on VCO gain (Ko) variation through the band of operation of the VCO. Thus, the reduction of transient responses requires additional efforts for PLL circuits having variable VCO gain.
Accordingly, it would be desirable to have a system and method for reducing transient responses occurring in a phase lock loop with variable oscillator gain.
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